This invention pertains generally to microwave signal sources, and more particularly to a microwave signal source comprising a digital frequency synthesizer using a single frequency offset technique with the frequency range of the signal source operating up to twice the highest operating frequency of a digital frequency divider in a phase-locked loop.
As is known in the art, microwave signal sources are a necessary element of communication and radar systems. Digital frequency synthesizers offer an attractive approach to generation of microwave multifrequency signals in applications not requiring continuous tuning capability. Digital frequency synthesizer architectures fall into two general categories. The first, known as direct frequency synthesizer architecture, is open-loop and utilizes frequency multipliers, dividers and mixers as key components. An advantage of such architecture is an extremely short frequency switching time. However, any known direct frequency synthesizer architecture generates more spurious frequencies and has more elements than the second category known as "indirect frequency synthesizer architecture."
Indirect frequency synthesizer architecture consists of digital phase-locked loops where the frequency of a voltage-controlled oscillator (VCO) is selected by the frequency division ratio of a programmable digital frequency divider (hereinafter also referred to as a "digital divider"). In applications where the frequency of the VCO output signal exceeds the highest frequency capability of the digital divider, the VCO output signal is heterodyned to a signal of suitable selected lower frequency for use in a phase-locked loop, known as an "offset loop." An advantage of known indirect frequency synthesizer architecture is that lower spurious levels are experienced due to the low-pass filter characteristics of phase-locked loops. A disadvantage of known indirect frequency synthesizer architecture is that a relatively long frequency switching time is realized because of the characteristics of known phase-locked loops. A further disadvantage of the indirect frequency synthesizer architecture using offset loops is that the frequency range of the output signal of the VCO is limited to the frequency range of the digital divider.
A conventional indirect frequency synthesizer employing a digital phase-lock loop consists essentially of a voltage-controlled oscillator (VCO) output signal phase-locked to a reference oscillator signal in a single offset digital phase-lock loop. A signal from an offset generator is used to heterodyne the full frequency range of the VCO output signal to lower intermediate frequencies (I.F.) within the frequency limits of the programmable digital frequency divider. The frequency of the offset generator signal is either slightly below the lowest frequency of the synthesizer output signal or slightly above the highest frequency of the synthesizer output signal in order to produce I.F. signals over the full frequency range of the synthesizer. The frequency of the VCO output signal is determined by the division ratio of the digital divider, such ratio being set by a suitable digital word applied to a decoder. The output signal of the digital divider and a reference frequency signal are connected to the two input ports of a digital phase/frequency detector, the output signal of which is amplified in a loop amplifier, filtered by a loop filter and applied to the tuning port of the VCO. The digital word that commands a specific VCO frequency sets the frequency division ratio of the digital divider to a value that, for the specific VCO frequency, produces a signal with a frequency equal to the frequency of the reference signal at the output of the digital divider. Following the application of a frequency select command, the frequency division ratio of the digital divider changes, causing the loop to unlock. Under such conditions the phase/frequency detector acts as a discriminator and generates a voltage that, following amplification and filtering, tunes the frequency of the VCO into a capture range of the loop. When the capture range is reached, the phase/frequency detector takes on the characteristics of a phase detector and generates an error voltage required for phase-lock. Such a frequency synthesizer can generate signals of equally-spaced frequencies, with the smallest spacing increment equal to the reference frequency.
The frequency range that the frequency synthesizer can generate is limited by the highest operating frequency of the programmable digital frequency divider. In applications where wider frequency ranges have to be generated this limitation is usually overcome by either using multiple frequency offset generators or by adding a higher frequency fixed digital divider (prescaler) before the programmable digital frequency divider.
The disadvantage of the multiple frequency offset generator is in its added level of complexity because the frequency range of the synthesizer signal has to be partitioned into bands equal to the maximum operating frequency range of the digital divider signal, and one offset frequency has to be synthesized for every band.
The addition of a prescaler before the digital divider introduces several disadvantages. If the frequency division ratio of the prescaler is K, then the total frequency division ratio is increased by by the factor K. In a second order loop (typically used in this type of application) a K-fold increase in the frequency division ratio reduces the highest realizable loop bandwidth by the factor .sqroot.K and reduces the highest realizable open-loop gain by the factor K (20 log K dB). The reduced open loop gain magnitude causes a commensurate reduction in the capability of the loop to degenerate FM noise. A reduction in the realizable loop bandwidth also increases the switching time when frequency is to be changed. Also, if the frequency division ratio of the prescaler is K, then the frequency of the reference oscillator signal also has to be reduced by the factor K so that the phase/frequency detector can operate with the same frequency signals at its two input ports. It is therefore desirable to increase the frequency range of the VCO output signal without increasing the frequency division ratio of the loop.